A5.6.6 Memory BehaviorThe Cortex-A55 core supports all the ARMv8 memory types.However, the following behaviors are simplified and so for best performance their use is not recommended:Write-Through
Memory that is marked as Write-Through cannot be cached on the data-side and doesnot make coherency requests. On the instruction-side, areas that are marked as Write-Through and Write-Back can be cached in the L1 instruction cache. However, onlyareas marked as Write-Back can be cached in the L2 cache or the L3 cache.
Mixed inner and outer cacheability
Memory that is not marked as inner and outer Write-Back cannot be cached on thedata-side and does not make coherency requests. This applies to the memory typeonly, and not to the allocation hints. All caches within the cluster are treated as beingpart of the inner cacheability domain
Hi,
The .above description is reference to cortex a55 trm file.
1)However, only areas marked as Write-Back can be cached in the L2 cache or the L3 cache.
how to understand this sentence? Does it mean that in this situation, the data and instruction cache from memory to L1 directly? How L1 access memory directly bypass L2?
2) This applies to the memory type only, and not to the allocation hints.
Does it mean if support cache allocation, the data can also be cached?
Thanks
Hi martin，
Many thanks for your explanation.
I have one more question, how does A55 achieve cache only at L1? By prefetcher buffer or allocate from memory directly? If A55 have prefetch buffer, why allocate data to L3 first, when prefetcher is right, then removed from L3 and allocated to L1.
I'd need to check specifically what the A55 does, but I would expect it to be allocated straight into L1 in this scenario.
Martin,
Thanks for your help!
From the A55 spec, L1 & L2 should both have some ways to allocate memory data directly, But I didn't find where has the detailed description.