My platform is a Cortex-A9 MPCore CPU, Sabre Lite(i.mx6).
I tried to count TLB miss so I implemented PMUEVENT to check micro TLB miss.
But PMUEVENT doesn't support the main TLB miss event.
In cortex-a9 RFP, "If there is a miss in main TLB, performs a hardware translation table walk.".
1. Can I count main TLB miss in OS level?
2. Any other way to count main TLB miss with merging PMUEVENT?
Read about Cortex-A9 processor implemented architectural events and Cortex-A9 specific events from the ARM Cortex‑A9 Technical Reference Manual,
11.4 Performance monitoring events.
Instruction micro TLB miss and Data micro TLB miss are implemented performance monitoring events in the Cortex A9.
If you use specific OS, implement API in OS environment (to access specific processor registers) or try to use implemented APIs.
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