I'm trying to find out what level is the out-most level of inner shareable domain. Is there any register to get this information? I want to know what inner shareable domain is in A53 big-LITTLE architecture. I find some articles that telling L1 and L2 belongs to inner shareable domain. However I can't find a register to indicate that. So is it possible to check shareable domain from registers?
And if both L1 and L2 cache belong to inner shareable, can I make such a configure: L1 cache policy is write-through, L2 cache policy is write-back? As I know, these configures are achieved by setting MAIR_ELx. By setting MAIR, we can set inner shareable domain to wrtie-back strategy. Does it means both L1 and L2 cache are set with write-back? Is it possible to set L1 dcache with write-through and L2 cache with write-back?
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