Arm Community
Site
Search
User
Site
Search
User
Groups
Arm Research
DesignStart
Education Hub
Graphics and Gaming
High Performance Computing
Innovation
Multimedia
Open Source Software and Platforms
Physical
Processors
Security
System
Software Tools
TrustZone for Armv8-M
中文社区
Blog
Announcements
Artificial Intelligence
Automotive
Healthcare
HPC
Infrastructure
Innovation
Internet of Things
Machine Learning
Mobile
Smart Homes
Wearables
Forums
All developer forums
IP Product forums
Tool & Software forums
Pelion IoT Platform
Support
Open a support case
Documentation
Downloads
Training
Arm Approved program
Arm Design Reviews
Community Help
More
Cancel
Developer Community
IP Products
Processors
Jump...
Cancel
Processors
Cortex-A / A-Profile forum
Cortex A8 Instruction Cycle Timing
Blogs
Forums
Videos & Files
Help
Jump...
Cancel
New
Replies
90 replies
Subscribers
275 subscribers
Views
64537 views
Users
0 members are here
Cortex-A
Related
Cortex A8 Instruction Cycle Timing
Offline
barney vardanyan
over 7 years ago
Note: This was originally posted on 17th March 2011 at
http://forums.arm.com
Hi) sorry for bad English
I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
but I have no idea how can do this work using that documantation(
Parents
Offline
Dung Tran
over 7 years ago
Note: This was originally posted on 28th June 2011 at
http://forums.arm.com
I am sorry because I am still confused. For example: ldm r1, {r2, r3}
Assuming that this instruction starts at the cycle n.
If this instruction took only 1 cycle, r2, r3 would be available at the cycle n + 3.
However, this instruction takes 2 cycle, so when are r2 and r3 available? (n + 3) or (n + 4)?
Cancel
Up
0
Down
Reply
Cancel
Reply
Offline
Dung Tran
over 7 years ago
Note: This was originally posted on 28th June 2011 at
http://forums.arm.com
I am sorry because I am still confused. For example: ldm r1, {r2, r3}
Assuming that this instruction starts at the cycle n.
If this instruction took only 1 cycle, r2, r3 would be available at the cycle n + 3.
However, this instruction takes 2 cycle, so when are r2 and r3 available? (n + 3) or (n + 4)?
Cancel
Up
0
Down
Reply
Cancel
Children
No data
More questions in this forum
By title
By date
By reply count
By view count
By most asked
By votes
By quality
Descending
Ascending
All recent questions
Unread questions
Questions you've participated in
Questions you've asked
Unanswered questions
Answered questions
Questions with suggested answers
Questions with no replies
Not Answered
Forum FAQs
0
ARM Community
712
views
0
replies
Started
5 days ago
by
Annie Cracknell
Not Answered
OSv guest encountering EC - "Unknown Reason" sync exception (ESR = 0x2000000) on Raspberry PI 4B host with KVM on
0
Raspberry Pi
Cortex-A72
Emulation & Virtualization
1909
views
5
replies
Latest
23 hours ago
by
Waldek
Not Answered
Data abort exception for unaligned access in Cortex A55
0
351
views
1
reply
Latest
2 days ago
by
Annie Cracknell
Not Answered
How To Swap From 32-bit Mode To 64-bit Mode In An Android that has ARMV8-A OS
0
18980
views
4
replies
Latest
7 days ago
by
42Bastian Schick
Answered
Which register excactly control the endiness in the EL0 data access? SPSR_EL1 or SCTLR_EL1?
0
AArch64
Armv8-A
AArch32
2090
views
2
replies
Latest
9 days ago
by
George_
>
View all questions in Cortex-A / A-Profile forum