I want to enable MMU and Cache to improve the performance of my arm cortex-A5 core.
I have gone through the Reference manual of arm cortex a5 and found the below step to enable mmu and cache
1.Disable cache, branch predictors
2. Invalidate cache and TLB
3. set translation table entries , point ttbr register to translation table.
4.enable cache, branch predictor
5. enable MMU.
1. I need help to understand how the translation table entries are defined.. If i choose 1MB section option then
how can i make entry for External flash memory which is of 16MB.
Here we have different memory regions, internal Ram(1MB), internal flash(4MB), External flash(16MB) and so on..
How can i define translation table entries for the above mentioned memory regions.
2. Translation tables are stored in main memory, here main memory is RAM ???
3 How can we check all the above steps working or not in trace32 ??
by executing the command cache.view i am able to see the cache content but i am unable to understand it.
Thanks in Advance.
First of all, read ARM Cortex-A series programmer's guide for ARMv7, chapter "The Memory Management Unit".
1) External flash memory directly or indirectly addressed (via flash controller)? First level translation table occupies 4096 32-bit entries in memory, one 32-bit entry for 1MB section. For 16MB of memory you have to configure 16 entries in the 1-level translation table. In the chapter "The Memory Management Unit" you can find examples of translation and entry configuration.
For example, code fragments (for Cortex A5 Atmel Sama5d2):
ALIGNED(16384) static uint32_t tlb; // translation table allocated in main memory
/* Reset table entries */ for (addr = 0; addr < 4096; addr++) tlb[addr] = 0;
/* 0x00000000: ROM */ tlb[0x000] = TTB_SECT_ADDR(0x00000000) | TTB_SECT_AP_READ_ONLY | TTB_SECT_DOMAIN(0xf) | TTB_SECT_EXEC | TTB_SECT_CACHEABLE_WB | TTB_TYPE_SECT;
/* 0x00100000: NFC SRAM */ tlb[0x001] = TTB_SECT_ADDR(0x00100000) | TTB_SECT_AP_FULL_ACCESS | TTB_SECT_DOMAIN(0xf) | TTB_SECT_EXEC | TTB_SECT_SHAREABLE_DEVICE | TTB_TYPE_SECT;
/* 0x00200000: SRAM */ tlb[0x002] = TTB_SECT_ADDR(0x00200000) | TTB_SECT_AP_FULL_ACCESS | TTB_SECT_DOMAIN(0xf) | TTB_SECT_EXEC | TTB_SECT_CACHEABLE_WB | TTB_TYPE_SECT;
2) Yes, RAM is main memory.
I will go through it.
Suppose we have two 512kb of SRAM region (SRAM0, SRAM1), do we need to make entry for them separately ?
The addresses you mentioned in the section field, are those physical address of the memory modules ?
Can you pls take some time and explain with a diagram of VA and PA mapping for the above entries you mentioned..
How the VA to PA translation takes place?
For example, code fragments (for Cortex A5 Atmel Sama5d2): ---> Can you give me the link for the source code and if there is any document.
Thanks you so much.
The addresses you mentioned in the section field, are those physical address of the memory modules ? - yes those are physical address of memory modules
I went through the programmers guide for cortex-A5, and its pretty clear now.
I thought to define Translation table entries for 1MB sections and give a try.. But check the below scenario
For 1MB SRAM with two sections of 512kb each, if 2 entries are made
tlb = sect(0x3ef00000) /* This is for SRAM0 */ Here we say section size is 1MB and when we define memory attributes, it will be applicable to 1MB area instead of 512KB?
And for the below SRAM1 area, same attributes will be applicable as it comes under the 1MB section for which attributes are defined above with SRAM0..
Then is it correct to do so.. or we need to go for small page sizes for 512KB or lower memory sizes.
tlb = sect(0x3ef80000) /* This is for SRAM1 */
coming to larger memory size flash 4MB, four entries can be made
tlb = sect(0x18000000) /* Each 1MB section will have its own attributes, correct ? */
tlb = sect(0x18100000)
tlb = sect(0x18200000)
tlb = sect(0x18300000)
When we say 1MB section , then one entry cannot be done for 128KB memory region ? In this case we need to go for small page size like 2 64kb ?
is my understanding correct Van.
tlb = sect(0x3ef00000) /* This is for SRAM0 */ - this is correct, in this case virtual addresses in range 0x00000000 - 0x000FFFFF are mapped to physical addresses in range 0x3EF00000 - 0x3EFFFFFF and also in this case SRAM0 and SRAM1 both are mapped into the tlb entry (512KB + 512KB = 1MB). Translation table entries of 1-level translation can't be smaller than 1 MB. If you want to divide this address space section to smaller chunks you have to define 2-level translation table and make entry from 1-level table to point to 2-level translation table. Further in 2-level translation table you can divide your address space into pages of size 64KB or 4KB.
tlb = sect(0x3ef80000) /* This is for SRAM1 */ - it is not correct
other definitions seems to be correct
If there is anything else, will get back to you.
Thank you so much Van.