Hello there,
I want to enable MMU and Cache to improve the performance of my arm cortex-A5 core.
I have gone through the Reference manual of arm cortex a5 and found the below step to enable mmu and cache
Steps :
1.Disable cache, branch predictors
2. Invalidate cache and TLB
3. set translation table entries , point ttbr register to translation table.
4.enable cache, branch predictor
5. enable MMU.
Queries
1. I need help to understand how the translation table entries are defined.. If i choose 1MB section option then
how can i make entry for External flash memory which is of 16MB.
Here we have different memory regions, internal Ram(1MB), internal flash(4MB), External flash(16MB) and so on..
How can i define translation table entries for the above mentioned memory regions.
2. Translation tables are stored in main memory, here main memory is RAM ???
3 How can we check all the above steps working or not in trace32 ??
by executing the command cache.view i am able to see the cache content but i am unable to understand it.
Thanks in Advance.
ZbinAhmed
The addresses you mentioned in the section field, are those physical address of the memory modules ? - yes those are physical address of memory modules
If you want to fundamentally understand the purpose of memory management I recommend you to read the book "Modern Operating Systems" Andrew S. Tanenbaum, particularly the chapter "Memory management".
Van,
I went through the programmers guide for cortex-A5, and its pretty clear now.
I thought to define Translation table entries for 1MB sections and give a try.. But check the below scenario
For 1MB SRAM with two sections of 512kb each, if 2 entries are made
tlb[0] = sect(0x3ef00000) /* This is for SRAM0 */ Here we say section size is 1MB and when we define memory attributes, it will be applicable to 1MB area instead of 512KB?
And for the below SRAM1 area, same attributes will be applicable as it comes under the 1MB section for which attributes are defined above with SRAM0..
Then is it correct to do so.. or we need to go for small page sizes for 512KB or lower memory sizes.
tlb[1] = sect(0x3ef80000) /* This is for SRAM1 */
coming to larger memory size flash 4MB, four entries can be made
tlb[2] = sect(0x18000000) /* Each 1MB section will have its own attributes, correct ? */
tlb[3] = sect(0x18100000)
tlb[4] = sect(0x18200000)
tlb[5] = sect(0x18300000)
Understanding:
When we say 1MB section , then one entry cannot be done for 128KB memory region ? In this case we need to go for small page size like 2 64kb ?
is my understanding correct Van.
Thanks.
tlb[0] = sect(0x3ef00000) /* This is for SRAM0 */ - this is correct, in this case virtual addresses in range 0x00000000 - 0x000FFFFF are mapped to physical addresses in range 0x3EF00000 - 0x3EFFFFFF and also in this case SRAM0 and SRAM1 both are mapped into the tlb[0] entry (512KB + 512KB = 1MB). Translation table entries of 1-level translation can't be smaller than 1 MB. If you want to divide this address space section to smaller chunks you have to define 2-level translation table and make entry from 1-level table to point to 2-level translation table. Further in 2-level translation table you can divide your address space into pages of size 64KB or 4KB.
tlb[1] = sect(0x3ef80000) /* This is for SRAM1 */ - it is not correct
other definitions seems to be correct
ok..
If there is anything else, will get back to you.
Thank you so much Van.
Hi Van,
I have made translation table entries, flashed the app and debugging it. And when i enable mmu, translation/section fault occurs.
The memory dump is getting locked ( all ? marks).
I am using 1MB section, so here we will have 4096 entries for L1 translation table.
Can i use any 'x' entry to hold information about any 'y' 1MB section ???
Way 1: starting from the address 0x0000_0000 to 0xFFFF_FFFF
entry[0x000] = sect[0x00000000 - 0x000FFFFF] //section 1
entry[0x001]= sect[0x00100000 - 0x001FFFFF] //section2
entry[0x002]= sect[0x00200000 - 0x002FFFFF] //section3
Way 2:
entry[0x000] = sect[0x18F00000 - 0x18FFFFFF]
entry[0x001]= sect[0x19000000 - 0x190FFFFF]
entry[0x002] = sect[0x19100000-0x191FFFFF]
Are the above mentioned ways valid ???
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0333h/Babicjaf.html
6.9.3. Translation fault
There are two types of translation fault:
A section translation fault occurs if:
The TLB tries to perform a page table walk but the page table walk is disabled by one of the PD0 or PD1 bits. For more details, see Hardware page table translation.
The TLB fetches a first level translation table descriptor, and this first level descriptor is invalid. This is the case when bits[1:0] of this descriptor are b00 or b11.
1. I have checked, It is not because of PD0 bit.
2. And for the underlined point, is it referring to 1st two lower bits of entry ?? ,
because i am using section type entry, the lower 2 bits are "10"
Can you please suggest something.
Thanks
Can you send the code with MMU configuration to my email (you can find email in my contacts)?