Hello there,
I want to enable MMU and Cache to improve the performance of my arm cortex-A5 core.
I have gone through the Reference manual of arm cortex a5 and found the below step to enable mmu and cache
Steps :
1.Disable cache, branch predictors
2. Invalidate cache and TLB
3. set translation table entries , point ttbr register to translation table.
4.enable cache, branch predictor
5. enable MMU.
Queries
1. I need help to understand how the translation table entries are defined.. If i choose 1MB section option then
how can i make entry for External flash memory which is of 16MB.
Here we have different memory regions, internal Ram(1MB), internal flash(4MB), External flash(16MB) and so on..
How can i define translation table entries for the above mentioned memory regions.
2. Translation tables are stored in main memory, here main memory is RAM ???
3 How can we check all the above steps working or not in trace32 ??
by executing the command cache.view i am able to see the cache content but i am unable to understand it.
Thanks in Advance.
ZbinAhmed
I have mentioned the address for RAM, ROM , in this case how we can map onto virtual memory? - very easy, just carefully map and make right configuration of attributes))
Is flat mapping enabled by default , even if we enable MMU, ? - If MMU is disabled then CPU operates by physical addresses (flat mapping), only if you enable MMU, CPU will operate by virtual addresses. Example code above was written for demo project, CPU in that case operates virtual addresses but with flat mapping configured in MMU translation table.
If flat mapping is enabled, then the VA for RAM will be same as the PA defined ? (0x3EF00000 - 0x3EFFFFFF) - Yes. When the MMU is disabled, all virtual addresses map directly to the corresponding physical address (a flat mapping).
What address goes in the section field in translation table entry ( 0x3ef00000) ??? - I can't understand this question(
For ROM, should there be multiple entries in Translation table or only one entry is required? - its your choice how multiple entries will be in the translation table, you can hide almost all addresses just writing zeros to table entries, but for example for 4MB ROM you have to map 4 entries of 1MB each for 1-level translation table.
Inside ROM, there are sections defined for boot code, application code and others, do we need to make entries for them? - I am not expert of writing tables for MMU (I only know how MMU works and translates addresses), but I think the answer is yes, you have to configure properly all pages that will be used during CPU operation.
Example of mapping:
Suppose we define memory for table
ALIGNED(16384) static uint32_t tlb[4096];
CPU generates VA = 0x0020 0404, high 12 bits (0x002) is the address of entry in 1-level translation table (in this example is the entry #2 in the table), low 20 bits (0x00404) will be used as offset in the page.
suppose TTBR = 0xFFFF 0000, this is the address of 1-level translation table, then
0xFFFF 0000 + (0x002 * 4) = 0xFFFF 0008 this is the address of entry in table, in turn entry gives us part of physical address and attributes for memory section
suppose we configure table entry #2 like:
tlb[0x002] = TTB_SECT_ADDR(0x00800000)| TTB_SECT_AP_FULL_ACCESS| TTB_SECT_DOMAIN(0xf)| TTB_SECT_EXEC| TTB_SECT_CACHEABLE_WB| TTB_TYPE_SECT;
then PA = 0x00800000 (high 12 bits of TTB_SECT_ADDR(0x00800000) ) + 0x00404 (offset in the page) = 0x00800404