Hello there,
I want to enable MMU and Cache to improve the performance of my arm cortex-A5 core.
I have gone through the Reference manual of arm cortex a5 and found the below step to enable mmu and cache
Steps :
1.Disable cache, branch predictors
2. Invalidate cache and TLB
3. set translation table entries , point ttbr register to translation table.
4.enable cache, branch predictor
5. enable MMU.
Queries
1. I need help to understand how the translation table entries are defined.. If i choose 1MB section option then
how can i make entry for External flash memory which is of 16MB.
Here we have different memory regions, internal Ram(1MB), internal flash(4MB), External flash(16MB) and so on..
How can i define translation table entries for the above mentioned memory regions.
2. Translation tables are stored in main memory, here main memory is RAM ???
3 How can we check all the above steps working or not in trace32 ??
by executing the command cache.view i am able to see the cache content but i am unable to understand it.
Thanks in Advance.
ZbinAhmed
First of all, read ARM Cortex-A series programmer's guide for ARMv7, chapter "The Memory Management Unit".
1) External flash memory directly or indirectly addressed (via flash controller)? First level translation table occupies 4096 32-bit entries in memory, one 32-bit entry for 1MB section. For 16MB of memory you have to configure 16 entries in the 1-level translation table. In the chapter "The Memory Management Unit" you can find examples of translation and entry configuration.
For example, code fragments (for Cortex A5 Atmel Sama5d2):
...
ALIGNED(16384) static uint32_t tlb[4096]; // translation table allocated in main memory
uint32_t addr;
/* Reset table entries */ for (addr = 0; addr < 4096; addr++) tlb[addr] = 0;
/* 0x00000000: ROM */ tlb[0x000] = TTB_SECT_ADDR(0x00000000) | TTB_SECT_AP_READ_ONLY | TTB_SECT_DOMAIN(0xf) | TTB_SECT_EXEC | TTB_SECT_CACHEABLE_WB | TTB_TYPE_SECT;
/* 0x00100000: NFC SRAM */ tlb[0x001] = TTB_SECT_ADDR(0x00100000) | TTB_SECT_AP_FULL_ACCESS | TTB_SECT_DOMAIN(0xf) | TTB_SECT_EXEC | TTB_SECT_SHAREABLE_DEVICE | TTB_TYPE_SECT;
/* 0x00200000: SRAM */ tlb[0x002] = TTB_SECT_ADDR(0x00200000) | TTB_SECT_AP_FULL_ACCESS | TTB_SECT_DOMAIN(0xf) | TTB_SECT_EXEC | TTB_SECT_CACHEABLE_WB | TTB_TYPE_SECT;
2) Yes, RAM is main memory.
Thanks van,
I will go through it.
Suppose we have two 512kb of SRAM region (SRAM0, SRAM1), do we need to make entry for them separately ?
The addresses you mentioned in the section field, are those physical address of the memory modules ?
Can you pls take some time and explain with a diagram of VA and PA mapping for the above entries you mentioned..
How the VA to PA translation takes place?
For example, code fragments (for Cortex A5 Atmel Sama5d2): ---> Can you give me the link for the source code and if there is any document.
Thanks you so much.
Suppose we have two 512kb of SRAM region (SRAM0, SRAM1), do we need to make entry for them separately? - it depends of your choice, you can configure this memory region using 2-level translation table with 4KB or 64KB pages.
The addresses you mentioned in the section field, are those physical address of the memory modules? - in the above example translation table entries are flat mappings, VA = PA.
How the VA to PA translation takes place? - Later I will write few examples of translation and post them into reply to this topic.
https://www.microchip.com/Developmenttools/ProductDetails/ATSAMA5D2C-XULT
Download IAR Software package 2.13 for EWARM from there, unpack and get the file "\target\sama5d2\board_support.c"
I have mentioned the address for RAM, ROM , in this case how we can map onto virtual memory ?
Is flat mapping enabled by default , even if we enable MMU, ?
If flat mapping is enabled, then the VA for RAM will be same as the PA defined ? (0x3EF00000 - 0x3EFFFFFF)
What address goes in the section field in translation table entry ( 0x3ef00000) ???
For ROM, should there be multiple entries in Translation table or only one entry is required?
Inside ROM, there are sections defined for boot code, application code and others, do we need to make entries for them ?
Thanks Van
I have mentioned the address for RAM, ROM , in this case how we can map onto virtual memory? - very easy, just carefully map and make right configuration of attributes))
Is flat mapping enabled by default , even if we enable MMU, ? - If MMU is disabled then CPU operates by physical addresses (flat mapping), only if you enable MMU, CPU will operate by virtual addresses. Example code above was written for demo project, CPU in that case operates virtual addresses but with flat mapping configured in MMU translation table.
If flat mapping is enabled, then the VA for RAM will be same as the PA defined ? (0x3EF00000 - 0x3EFFFFFF) - Yes. When the MMU is disabled, all virtual addresses map directly to the corresponding physical address (a flat mapping).
What address goes in the section field in translation table entry ( 0x3ef00000) ??? - I can't understand this question(
For ROM, should there be multiple entries in Translation table or only one entry is required? - its your choice how multiple entries will be in the translation table, you can hide almost all addresses just writing zeros to table entries, but for example for 4MB ROM you have to map 4 entries of 1MB each for 1-level translation table.
Inside ROM, there are sections defined for boot code, application code and others, do we need to make entries for them? - I am not expert of writing tables for MMU (I only know how MMU works and translates addresses), but I think the answer is yes, you have to configure properly all pages that will be used during CPU operation.
Example of mapping:
Suppose we define memory for table
ALIGNED(16384) static uint32_t tlb[4096];
CPU generates VA = 0x0020 0404, high 12 bits (0x002) is the address of entry in 1-level translation table (in this example is the entry #2 in the table), low 20 bits (0x00404) will be used as offset in the page.
suppose TTBR = 0xFFFF 0000, this is the address of 1-level translation table, then
0xFFFF 0000 + (0x002 * 4) = 0xFFFF 0008 this is the address of entry in table, in turn entry gives us part of physical address and attributes for memory section
suppose we configure table entry #2 like:
tlb[0x002] = TTB_SECT_ADDR(0x00800000)| TTB_SECT_AP_FULL_ACCESS| TTB_SECT_DOMAIN(0xf)| TTB_SECT_EXEC| TTB_SECT_CACHEABLE_WB| TTB_TYPE_SECT;
then PA = 0x00800000 (high 12 bits of TTB_SECT_ADDR(0x00800000) ) + 0x00404 (offset in the page) = 0x00800404
View all questions in Cortex-A / A-Profile forum