when we says "Cortex-A53 processor simplifies the coherency logic by downgrading memory to non Cache able if it is marked as Inner Write-Through or outer Write though" what is excatly this means ..Is CA53 treats WT memory as non cache able ?
Correct. Write Through memory is supported by the Arm Architecture, but is not implemented on all CPUs. One method to handle regions of memory marked as write through is to downgrade them to Normal non-cacheable accesses.