Cortex-M7: Force Precise Exception on Bus Fault

I was wondering if anyone knows of a way to force the Cortex-M7 CPU to take a precise exception when a bus fault occurs. I'm writing an application that requires the bus fault handler to know the exact address of the instruction that generated the bus fault so it can take remedial action. Apparently this is possible in the Cortex-M3 and M4 CPUs by setting the DISDEFWBUF bit to 1 in the Aux Control Register, which disables the load/store buffer. I can't seem to find an analogous feature in the M7 (perhaps because the M7 has a cache and the M3/4 don't?). I would like to avoid writing code to search back through instructions to find one that may have caused an exception because that seems like it could get complicated. I'd also like to avoid disabling the cache.

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  • Hi there,
    Since the Cortex-M7 D-cache operates as write back mode by default (if enabled), even if the write buffer is disabled you cannot locate the exact point where there transfer is issued. As a result, the DISDEFWBUF feature is not going to be any use in Cortex-M7. Also, AXI interface supports multiple outstanding transfers, so unfortunately I can't think of any way to force bus faults to be precise.
    regards,
    Joseph
  • Hi ,

    Sorry for digging up such old post, but while trying to find solution to a close issue like the one reported by I decided to reply to your answer. 

    As I noticed in my recent investigation, Cortex-M7 processors doesn't have any mechanism to force bus faults to be precise, which I understood by reading your explanation above. However, in my case, I am trying to know the exact address of an instruction that generated a bus fault while trying to write to the System Control Space (SCS) from an unprivileged mode. Looking to Cortex M7 TRM, SCS is located on PPB ROM Table. Following my understanding of Cortex-M7 functional diagram (Figure 1-3), there isn't a path between the Store Buffer (STB) and the PPB ROM table. Therefore, is there any other way and reason for me to be able to force a precise bus fault in this specific situation ? 

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  • Hi ,

    Sorry for digging up such old post, but while trying to find solution to a close issue like the one reported by I decided to reply to your answer. 

    As I noticed in my recent investigation, Cortex-M7 processors doesn't have any mechanism to force bus faults to be precise, which I understood by reading your explanation above. However, in my case, I am trying to know the exact address of an instruction that generated a bus fault while trying to write to the System Control Space (SCS) from an unprivileged mode. Looking to Cortex M7 TRM, SCS is located on PPB ROM Table. Following my understanding of Cortex-M7 functional diagram (Figure 1-3), there isn't a path between the Store Buffer (STB) and the PPB ROM table. Therefore, is there any other way and reason for me to be able to force a precise bus fault in this specific situation ? 

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