The Cortex-A9 MPCore Technical Reference Manual Revision: r4p1
describes the Bit 0 of scu-control-register as 0 SCU enable 1 SCU disable. (this is Version i of the manual)
In Version g of the manual ist the other way round (1 SCU enable 0 SCU disable).
is the new or the old version correct?
There is no mention of this change in the Revision History of the manual.
It looks like developer.arm.com have older version of A9 MPCore TRM.. The newer version is only at infocenter.arm.com http://infocenter.arm.com/help/topic/com.arm.doc.100486_0401_10_en/cortex_a9_mpcore_trm_100486_0401_10_en.pdf
and it have description of this bit fixed. And I can confirm that 1 *enables* SCU.