Currently I'm using SPE to trace program execution flow (like Intel PT).
However, since it is a feature of performance measurement, it seems not able to record all branch instructions.
See Chapter D9.3 of Armv8 manual, the interval counter is PMSICR_EL1.COUNT. When it decreases to zero, a record would be poped, and the counter would be reseted according to PMSIRR_EL1.INTERVAL and PMSIRR_EL1.RND.
Due to Chapter D13.6.10, the Interval (bits [11:8]) of PMSIDR_EL1 gives the recommended minimum sampling interval (minimum 256).
Since the PMSIRR_EL1.INTERVAL can only control bits [31:8] of PMSICR_EL1.COUNT, that means we will have at least 256 operations interval between 2 records.
Hoping for no interval, I try to set PMSIRR_EL1.INTERVAL to 0. Theoretically, in this case PMSICR_EL1.COUNT would keep zero when each instruction is executing, thus it would record all branch instructions for me.
In consequence, it seems does not work. In perf auxtrace there is more records than case setting interval to 256, but apparently it does not contain all branch instructions.
It seems no explanation in manual when PMSIRR_EL1.INTERVAL set to 0, how would SPE behave in this case ?
I am not quite sure which version v8 architecture you are using. In the latest v8 architecture, there is below description for PMSIRR_EL1.INTERVAL
INTERVAL, bits [31:8]Bits [31:8] of the PMSICR_EL1 interval counter reload value. Software must set this to a non-zerovalue. If software sets this to zero, an UNKNOWN sampling interval is used. Software should set thisto a value greater than the minimum indicated by PMSIDR_EL1.Interval.On a Warm reset, this field resets to an architecturally UNKNOWN value.
It seems that PMISRR_EL1.INTERVAL should not be set to zero.
Thanks. Which document did you refer to? (and which page if you remember)
You could download the document from below link. On page 4025, you will find the description for the PMSIRR_EL1
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