Hi the master is connected to axi-interconnect and two slaves(A and B) are connected to axi-interconnect.The master send a write transcation(AA) to slave A and then send a write transcation(BB) to slave B with same ID.the two transcations with the same ID, axi mention that the master should receive A1's response and then B1's response from axi-interconnect..
Now,i have some question about that.the two transcations must arrive to slave A and then arrive to slave B?is it possible that the transcations can arrive to two slaves out of order and axi-interconnect. send their response to master in order ?
Obviously if you are using the same ID, the master must issue all the WDATA for transaction AA before it send the first WDATA for transaction BB, so the only reason slave B might see WDATA before slave A would be if there was lots more registering on the path from the interconnect to slave B compared to registering on the path to slave A (the AA data will all have been sent by the interconnect before it can send any data to for BB).
However even if slave A has received all the AA data before slave B sees any BB data, there could be a long delay before slave A returns the BRESP for AA, meaning slave B could return the BRESP for BB first. In that case the interconnect would need to stall the BB BRESP response until the AA BRESP has been received, so the master will always see the correctly ordered responses.
Thanks for replyYou mentioned that the AA data will all have been sent by the interconnect before it can send any data to for BB.Q1:does It mean that the interconnect ordering must be same as master ordering? I can not find this statement in the specIn axi spec(ARM IHI 0022C )it mention that The order of transactions in the same direction with the same ID to a Device is preserved.Q2:What is the meaning of same direction?it means same slave?the spec also mention that The order of transactions in the same direction with the same ID to overlapping addresses is preserved.Q3:What is the meaning of overlapping addresses ?Q4:assume we have a portA on the interconnect, and the masterA is connected to portA. When masterA send the transcation to portA, and then portA will send the transcation internally. Does it mean that portA is master and slave too?I am confused with interconnect ordering statement in the specThanks a lot!!
The AXI spec tried to simplify itself in that it only describes a point-to-point connection between a master and a slave. How you then build an interconnect to connect multiple masters to multiple slaves is left up to you, the idea being that it gives you a lot of flexibility in how you might do this, and all the interconnect needs to ensure is that any protocol requirements are met at its external ports.
So you will have external AXI masters connected to AXI slave interfaces on the interconnect (where the interconnect needs to ensure all AXI slave protocol requirements are met), and then you will have AXI master interfaces on the interconnect connected to external AXI slaves (where the interconnect then needs to meet any AXI master protocol requirements are met).
Q1. As above, the AXI spec doesn't describe rules for within the interconnect, only at the AXI slave and master interfaces on that interconnect. So if the interconnect was routing transactions to two different slaves, those slaves could complete those transfers in a different order than the original master required, but the interconnect logic then needs to re-order those transaction completions if the protocol requires it (for transactions using the same ID).
Q2. Same direction here means reads or writes. Read and write operations are performed with no ordering requirements between them (other than for exclusive sequences), so the spec is stating that a series of write transactions using the same ID will complete in the order they were issued, or a series of read transactions using the same ID will complete in the order they were issued.
Q3. Overlapping addresses. An AXI transaction states a start address, a number of transfers, and by how much each transfer increments on the last one (unless it is a FIXED burst), so taken together these 3 controls gives you a range of byte addresses being accessed. So you could have 2 separate transactions, with different start address, length and width values, which have byte addresses that appear in both ranges, so "overlapping".
Q4. Hopefully answered above, "masterA" connects to "portA" on your interconnect, and this "portA" will be an AXI slave.
Yes, it can be confusing about thinking what components have master ports and which have slave ports, so just think that in a chain of components, the upstream interface on each point-to-point connection in the chain is a master port and the downstream interface is a slave port.
So perhaps you have an AXI master connected via an AXI-AXI bridge for timing purposes, then maybe an AXI downsizer to reduce the data width from 64 bits to 32 bits, and then an interconnect, through maybe another AXI-AXI bridge and finally an AXI slave, at each step you have an AXI master interface driving an AXI slave interface. The AXI master connects to an AXI slave port on the AXI-AXI bridge, then an AXI master port on the AXI-AXI bridge drives an AXI slave port on the AXI downsizer, then an AXI master port on the downsizer drives an AXI slave port on the interconnect, and so on down the chain of connected components.
While the communication over an AXI bus is between a single master and a single slave, the specification includes detailed description and signals to include N:M interconnects, able to extend the bus to topologies with more masters and slaves.
I'm not sure where in the AXI protocol you see "detailed descriptions" of how to implement topologies with more masters and slaves as the AXI protocol is written to describe point-to-point master-slave connections.
The only area I can think you might be referring to us the section on "Transaction ordering", which talks about how masters and slaves handle transactions with different IDs, and how interconnects append bits to the master issued IDs. If this is what you were describing, it isn't much detail on how to implement the interconnects, it is only explaining why the IDs the slave sees might not be the same ones the masters issue.
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