Hi AllI have two questions.Q1:is it ok that WVALID , WREADY and BVALID assert at the same cycle?Thanks!Q2: what is different between out of order and data interleaving ?Thanks!
I prefer AXI lite for most situations. Just send the address with the data, and it can still support one data transfer per cycle. Back pressure is needed and I’m ok with some slaves supporting simultaneous reads and writes.
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