Hi AllI have two questions.Q1:is it ok that WVALID , WREADY and BVALID assert at the same cycle?Thanks!Q2: what is different between out of order and data interleaving ?Thanks!
WVALID, WREADY and BVALID can all be asserted in the same cycle, BUT NOT for the same transactions. See the section in the AXI protocol titled "Dependencies between channel handshake signals .
The write interleaving means a master will issue write data separately for one transaction. The out-of-order means a relationship between address PupilPath Login and data. On an AXI bus, IDs indicates the correspondence between addresses and data. Therefore, the order of addresses and data is independent.