How to stop coresight sink on CPU exception

We are collecting trace in trace buffer (ETB) , looking for the way to stop the sink to collect or stopping the source on CPU exception.

How it can be configured for the same?

Regards,

Sudipta

  • Hi are you still looking for an answer to this question?

  • The systems shown here demonstrate the most basic configurations of a CoreSight system. More complex systems might involve clusters of processors, multiple clock domains, etc .This configuration provides no trace capabilities. The DAP shown here is configured with a combined Serial Wire and JTAG external interface, and APB internal debug access. The Debug APB connects using an APB-Interconnect to configure the CTI and access the processor. The CTI supports triggering of the processor from a designated resource, and enables connection to additional triggering resources if this example is integrated into a larger system.

  • "Sources" generate a compressed stream representing the processor instruction path based on tracing scenarios as configured by users. From there the stream flows through the coresight system (via ATB bus)  alaskasworld using links that are connecting the emanating source to a sink(s). Sinks serve as endpoints to the coresight implementation, either storing the compressed stream in a memory buffer or creating an interface to the outside world where data can be transferred to a host without fear of filling up the onboard coresight memory buffer.

  • Hi do the replies below help to answer your question? If so, please mark one as accepted. Many thanks.

  • The DAP appeared here is arranged with a joined Serial Wire and JTAG outside interface, sinks fill in as endpoints to the coresight execution and APB inward troubleshoot access. Either putting away the compacted stream in a memory cradle or making an interface to the rest of the reality where information can be moved to a host unafraid of topping off the locally available coresight memory support. The Debug APB associates utilizing an APB-Interconnect to arrange the CTI and access the processor.

    UPSers

More questions in this forum