Program Counter, Stack Pointer and Link Register Status During an Interrupt Service in ARM based Processors

what happens when interrupt comes to program counter stck pointer and link register in ARM based Processor Architeture ?

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  • Which processor?

    For Armv7-A and earlier, assuming the exception is taken:

    • The PC will be set to the appropriate exception vector
    • SPSR_<mode> will be set to the CPSR value immediately before the exception
    • CPSR will be update with the correct mode and instruction set.
    • LR_<mode> will be set to the exception return address
    • SP will now select SP_<mode>
    Where <mode> is the exception mode.  So for an interrupt, it would be SPSR_irq, LR_irp and SP_irq.
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  • Which processor?

    For Armv7-A and earlier, assuming the exception is taken:

    • The PC will be set to the appropriate exception vector
    • SPSR_<mode> will be set to the CPSR value immediately before the exception
    • CPSR will be update with the correct mode and instruction set.
    • LR_<mode> will be set to the exception return address
    • SP will now select SP_<mode>
    Where <mode> is the exception mode.  So for an interrupt, it would be SPSR_irq, LR_irp and SP_irq.
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