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Does TLB save level-1 page directory entries?

Dong Luo
Offline over 6 years ago
Note: This was originally posted on 18th March 2009 at http://forums.arm.com

Hi All,
In ARM1176, does TLB save level-1 page directory entries? I know that section's descriptor is saved in level-1 page table and TLB saves section's descriptor. Besides section's descriptor, there are page directory entries in level-1 page table, which is used to point to level-2 page tables. So, my question is: does TLB save level-1 page directory entries? Can anybody clarify the question for me? Thanks in advance.
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  • 0 Offline over 6 years ago
    Note: This was originally posted on 6th June 2009 at http://forums.arm.com

    If you want to make it faster to do sequential L2 page lookups based on an L1 parent page entry the usual recommended solution is to enable outer cacheability for the pagetable walks. If you have a L2 cache configured as an outer cache then that can store data corresponding to the L1 and L2 pagetable memory - which can make pagetable walks significantly faster.

    ARMv6 doesn't allow pagetable walks to be cached in the L1 caches - but ARMv7 does, although microarchitecturally not all processors support it.
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  • 0 Offline over 6 years ago
    Note: This was originally posted on 6th June 2009 at http://forums.arm.com

    If you want to make it faster to do sequential L2 page lookups based on an L1 parent page entry the usual recommended solution is to enable outer cacheability for the pagetable walks. If you have a L2 cache configured as an outer cache then that can store data corresponding to the L1 and L2 pagetable memory - which can make pagetable walks significantly faster.

    ARMv6 doesn't allow pagetable walks to be cached in the L1 caches - but ARMv7 does, although microarchitecturally not all processors support it.
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