• State Accepted Answer
  • +1 person also asked this people also asked this
  • Replies 9 replies
  • Subscribers 2 subscribers
  • Views 3486 views
  • Users 0 members are here
Related

Of exceptions and aborts..

Felix Varghese
Offline over 6 years ago
Note: This was originally posted on 21st January 2009 at http://forums.arm.com

The ARM reference manual specifies sometimes MOV PC,R14 and sometimes SUBS PC,R14, #4 for returning from exceptions. But they have not mentioned why. Can somebdy expain?
Also, when exactly does the PC get incremented? During the Fetch ?
And exactly when (Fetching / Decoding / Executing) does an exception get generated?
Does an undefined instruction get generated when the instruction is decoded or when it is executed?
What about Data and Prefetch aborts?
Parents
  • 0 Offline over 6 years ago
    Note: This was originally posted on 22nd January 2009 at http://forums.arm.com

    The ARM reference manual specifies sometimes MOV PC,R14 and sometimes SUBS PC,R14, #4 for returning from exceptions. But they have not mentioned why. Can somebdy expain?

    It is historical.  Due to how very early ARMs were designed, the LR value produced for certain exceptions was always off by a fixed amount.  This was a way of saving gates, at a time when gates were expensive.  The offset has been maintianed ever since for software compatibility.

    Also, when exactly does the PC get incremented? During the Fetch ?

    On an ARM7, the PC points at the instruction being fetched.  So, when in ARM state...

      Instruction being Executed  PC-8
      Instruction being Decoded PC -4
      Instruction being Fetched  PC

    And exactly when (Fetching / Decoding / Executing) does an exception get generated?

    Depends on the exception type.

    Does an undefined instruction get generated when the instruction is decoded or when it is executed?
    What about Data and Prefetch aborts?

    An undefined instruction would be recognised at the decode stage - but would only be taken if it reaches the execute stage.  This is because the preceeding instruction could be a branch (or similar), meaning the undefined instruction would never be executed.

    Similarly, prefetch aborts are detected during fetch.  but only taken if it reaches the execute stage.

    For data aborts the story is more complicated, but it will be during or after the execute stage.
Reply
  • 0 Offline over 6 years ago
    Note: This was originally posted on 22nd January 2009 at http://forums.arm.com

    The ARM reference manual specifies sometimes MOV PC,R14 and sometimes SUBS PC,R14, #4 for returning from exceptions. But they have not mentioned why. Can somebdy expain?

    It is historical.  Due to how very early ARMs were designed, the LR value produced for certain exceptions was always off by a fixed amount.  This was a way of saving gates, at a time when gates were expensive.  The offset has been maintianed ever since for software compatibility.

    Also, when exactly does the PC get incremented? During the Fetch ?

    On an ARM7, the PC points at the instruction being fetched.  So, when in ARM state...

      Instruction being Executed  PC-8
      Instruction being Decoded PC -4
      Instruction being Fetched  PC

    And exactly when (Fetching / Decoding / Executing) does an exception get generated?

    Depends on the exception type.

    Does an undefined instruction get generated when the instruction is decoded or when it is executed?
    What about Data and Prefetch aborts?

    An undefined instruction would be recognised at the decode stage - but would only be taken if it reaches the execute stage.  This is because the preceeding instruction could be a branch (or similar), meaning the undefined instruction would never be executed.

    Similarly, prefetch aborts are detected during fetch.  but only taken if it reaches the execute stage.

    For data aborts the story is more complicated, but it will be during or after the execute stage.
Children
No data
More questions in this forum

View all questions in Classic processors forum