For the last weeks, I have been trying to get this new version to work. I did the same as with the previous version and now it is running on the Xilinx Nexys4. However, honestly I do not have any idea how to get the debugging to work. I defined the pins for SWD and connected to an Segger J-Link, but no connection was possible. There is the configuration option ‘define ARM_CMSDK_INCLUDE_JTAG. In removed this, no success. I changed to ‘define ARM_CMSDK_INCLUDE_SWD, no success. I am running out of ideas.
It seems I am missing something important.
Ok, I put the code from user_partition into my design and added the necessary connections. Unfortunately, the result remains the same.
A few things to check:
1) Check reset type to System Reset Request to see if it helps
2) I think the SWJ option can be uncheck as the Cortex-M0 DAP don't have protocol switching
3) Connection of SYSRESETREQ (System Reset Request) - can it generate a system reset?
4) JTAG/SWD clock constraints in synthesis, is it missing?
Hope it helps.
Another suggestion I've had is that maybe there is a clocking or reset with the core domain (since the DAP ID registers are in the SWCLK domain), affecting wither the core or the CDBGPWRUPREQ/CSYSPWRUPREQ and the corresponding acknowledge signals.
If you carry on with ULINKPro for now (we should follow the JLINK problem later), it will be useful to enable the logging:
Dear Sean, dear Joseph,
I solved parts of the problem on Saturday:
your suggestion with the CDBGPWRUPREQ to CDBGPWRUPACK loopback was right.
I copied the code, but forgot the CDBGPWRUPREQ connection.
So I had
.CDBGPWRUPREQ (), .CDBGPWRUPACK (CDBGPWRUPACK),
.CDBGPWRUPREQ (CDBGPWRUPREQ), .CDBGPWRUPACK (CDBGPWRUPACK),
I am now able to download and debug.
I will now try with J-Link and then do the next steps.
I am very grateful for you help and support.