Hello together, I am little bit confused regarding to the Cortex-M0DS comparability to Altera FPGAs.
On one hand, according to the information out of the white paper An introduction to ARM Cortex-M0 Design Start it must be possible to run the Cortex-M0 DS on an Altera FPGA because the DesignStart DesignKit deliver a synthesizable Verilog Version of the processor.
On the other hand till now I only find Master Thesis or Step by Step Guides like (STEP BY STEP GUIDE TO IMPLEMENTING THE CORTEX-M0 USING A NEXYS2 FPGA BOARD) which uses development boards based on Xilinx FPGAs.
So my questions are:
Thank you and best regards
>Is it possible to use the Cortex-M0 DesignStart with an Altera FPGA?
>Are there papers (Step by Step guides) which describes a usage of the DesignStart in combination with an Altera FPGA available?
Our MPS2+ FPGA board software package comes with an example project for Cortex-M0 DesignStart.
>Why will ARM deliver a Prototype-board based on an ARM FPGA instead of an Xilinx FPGA?
I guess you mean Altera FPGA. From memory (hope I got this right), when we designed MPS2, Altera Cyclone 5 was selected due to:
- partial reconfiguration
- low cost and availability
- FPGA image encryption support
- FPGA size
But today both XiIinx and Altera low cost FPGAs can met these technical requirements.
Hope this helps.
To help answer your questions, ARM ported CM0-DesignStart to our own FPGA board called MPS2 (which was then superseded by a larger FPGA capacity version called MPS2+). The reason we used this board was it was already available before we released CM0-DesignStart and we had previously ported other Cortex-M cores to that platform. (This platform is Altera based). see www.arm.com/mps
On the MPS2+ platform we partitioned the FPGA into 2 sections (1) CPU+ debug, which is fixed+encrypted and (2) User area, which is modifiable.
You could take the Cortex-M0 netlist from the CM0-DesignStart simulation world and target any FPGA technology (Xilinx or Altera) , ARM choose our own FPGA platform. The key difference here is if you take the netlist from the simulation world it would not have any debug, debug (my this I mean JTAG interface) is only available on the MPS2+ platform.
As Joseph mention below we have step by step guides for our platform, but not for generic FPGA platforms, however saying that some engineers have used their initiative and ported CM0-DesignStart to other platforms, like the one you mentioned above and I also saw someone was working on porting CM0-DesignStart to Digilient's Arty FPGA board (Xilinx based). We don't have guides for these platforms as the work was not done by us.
Hope that makes sense.
Thank you Joseph and Liam for the detailed answers!
I like the response time and the quality in this community!!!
I don't know what your HDL skills are but there is example code that might help you get started. Look in Digilent's Project Vault. You may have to read through a few projects to find examples specific to your current project but a lot of it is there. Don't understand basic digital design? That's a problem when you are coding in HDL only. You will have to understand how to read data sheets and timing diagrams.