I'm following the Cortex®-M0 DesignStart Eval FPGA User guide to do the FPGA Build Flow.
I follow below steps using Quartus Prime Lite Edition, with device - Cyclone V 5CEBA9F31C8
a. Select File > Open Project and navigate to the project file: RevC/SMM_M0DS/synthesis/SMM_M0DS_AN387.qpfb. Select Processing > Start Compilation
I got error in compilation fitter stage (Error 170012 Fitter requires 12085 LABs to implement the design, but the device contains only 11356 LABs)
I didn't do any modification, and the utilization rate of others like DSP/PLLs are all normal.
According to the user guide, the default design only utilize 10% of LUTs.
May I know if I missed any settings or configurations? Or it is Quartus version issue?
Thank you in advance for helping.