Does the DesignStart FPGA Cortex-M1/M3 support SWD multi-drop?

I am instantiating both a Cortex-M1 and a Cortex-M3 in a Xilinx 7-series FPGA and need SWD access to both cores.

Do these cores support SWD multi-drop? If so, is there a reference design - or just any design hints - available?