Does the DesignStart FPGA Cortex-M1/M3 support SWD multi-drop?

I am instantiating both a Cortex-M1 and a Cortex-M3 in a Xilinx 7-series FPGA and need SWD access to both cores.

Do these cores support SWD multi-drop? If so, is there a reference design - or just any design hints - available?

Parents
  • The stand-alone DAPs which come as part of these processors do not include multi-drop.

    If you have connected the processor to a full CoreSight DAP, or have constructed a DAP from discrete parts, then it is possible that you support multi-drop depending on which DP component is included.

    Essentially you we need additional components (available via CoreSight) to be able to instantiate both processors and communicate via SWD. 

Reply
  • The stand-alone DAPs which come as part of these processors do not include multi-drop.

    If you have connected the processor to a full CoreSight DAP, or have constructed a DAP from discrete parts, then it is possible that you support multi-drop depending on which DP component is included.

    Essentially you we need additional components (available via CoreSight) to be able to instantiate both processors and communicate via SWD. 

Children
No data