I am evaluating the SWD-Port of the Cortex-M0 Designstart using the obfuscated component of the Eval distribution AT510-MN-80001-r2p0-00rel in a Modelsim Simulation.
For that purpose I composed a minimal system with ROM, RAM and ROMTABLE. It runs a test-software which shows activities as expected on the AHB-Lite Bus.
Then I wrote a testbench to communicate with the Cortex-A0 via SWD wich performs the following steps according to the ARM® Debug InterfaceArchitecture Specification:
Thus my question is whether the used version of the obfuscated Cortex-M0 supports connection to a Mem-AP. As far as I understood the docs it does.
If it supports the AP, can anybody tell me, whats wrong with my register read/write sequence? Or did I make an error in my system design? Below an overview of the system is shown:
Thank you for your replies,Bernhard.
Thank you for your detailed explainations which helped me to find the error. In my SWD-test-process I found an error in the function which writes the DAP-Registers. Now it ist working fine as you can see in this timing:
It shows the following steps:(1) Reset of the SWD-Interface.(2) Read the DPIDIR of the Debug port which returns the correct value 0x0bb11477.(3) Activate CSYSPWRUPREQ and CDBGPWRUPREQ by writing 0x50000000 to the CTRL/STAT register of the DP.(4) Subsequent read of the CTRL/STAT register shows that CSYSPWRUPACK and CDBGPWRUPACK are set.(5) Write 0x000000f0 to the SELECT register of the DP which prepares to read IDR in AP0.(6) Read the IDR register of AP0, the value ist returnd in the next step.(7) Read the RDBUFF register of DP to get the value from IDR read. It shows the correct value 0x04770021
The system I am using is shown in my initial request at the top of this thread.