SWD: Cannot connect to MEM-AP on Cortex-M0 Designstart Eval

I am evaluating the SWD-Port of the Cortex-M0 Designstart using the obfuscated component of the Eval distribution AT510-MN-80001-r2p0-00rel in a Modelsim Simulation.

For that purpose I composed a minimal system with ROM, RAM and ROMTABLE. It runs a test-software which shows activities as expected on the AHB-Lite Bus.

Then I wrote a testbench to communicate with the Cortex-A0 via SWD wich performs the following steps according to the ARM® Debug Interface
Architecture Specification:

  1. Reset the SWD-Line during 50 SWCLK cycles with SWDIO High, then sending "0111100111100111" followed by another 50 cycles with SWDIO High.
  2. The subsequent reading of the DPIDR Register delivers the expected value 0x0BB11477.
  3. Next I tried to activate the power for system and debug by writing Ones into the bits CDBGPWRUPREQ and CSYSPWRUPREQ Bits of the Control/Status Register.
    (Writing value 0x50000000 to Control/Status).
    Unfortunately a following read of the Control/Status Register delivers the value 0x00000000 and not (as expected according to the ARM® Debug Interface
    Architecture Specification) the value 0xf0000000 (which would show the ACKs for power requests).
    Writing the value 0xf0000000 instead to the Control/Status Register did help to get 0xf0000000 in the readback of the Control/Status Register (which should
    signal that CDBGPWRUPREQ, CDBGPWRUPACK, CSYSPWRUPREQ and CSYSPWRUPACK are all set).
  4. Now I tried to connect to the Mem-AP.
    I wrote the SELECT Register with value 0x000000f0 to select the most upper bank of AP0.
    Then I did read the AP-IDR Register followed by a read of the DP-RDBUFF Register to get then IDR value. But the read returns always value 0x00000000,
    even when I changed the AP number.

Thus my question is whether the used version of the obfuscated Cortex-M0 supports connection to a Mem-AP. As far as I understood the docs it does.

If it supports the AP, can anybody tell me, whats wrong with my register read/write sequence? Or did I make an error in my system design? Below an overview of the system is shown:

Thank you for your replies,
Bernhard.