After getting frustrated with the Xilinx design start guide I created a minimal SoC implementation of CM3 using fusesoc. It currently runs on Arty but could be made to run on other FPGAs that have a fusesoc supported backend.
Both the Xilinx encrypted core and the obsfucated core are supported so it will run on other FPGAs as well (at a lower freq). It also includes a Verilated model for simulation.
Hope this helps someone!
PS: If there are any FPGA experts I could really using some help on the timing closure. Currently the encrypted model runs up to ~40MHz but I think this could be improved.