what is the extra FPGA utilization of debug/trace features in Cortex-M3 Xilinx edition

Hi,

Im integrating the COrtex M3 in our system.

I see there are few options for debug level and trace level configurations in Vivado.

What is the extra FPGA utilization (FFs, LUTs,..) according to the configured debug/trace level?

Thanks! 

Yonathan