Hi AllI have few questions about axiQ1:is it possible that WVALID , WREADY and BVALID assert at the same cycle?Q2: what is different between out of order and data interleaving ?Q3: is it possible that write transaction can happen all time in axi? i mean no idle timeThanks!
Any comment for that?Thanks
Hopefully I've already answered your first 2 questions in my reply to your earlier posting.
Q3. Yes, you can have back to back write transactions with no idle cycles in between them.
As the master will indicate how many data transfers there are in each transaction using the ARLEN bus, the slave knows when one sequence of data transfers ends and the next one starts. The slave will also see the WLAST signal asserted by the master for the final WDATA transfer in each transaction, so it can choose whether to count the AWLEN number of transfers received, or it can just look for WLAST being asserted.
So no need for any idle cycles in between the end of one data sequence and the start of the next.