make compile SIMULATOR=ius DSM=yes
xmvlog: *W,NOTIND: unable to access -INCDIR ../../../../cortexm3_rtl/logical/cm3_tpiu/verilog (No such file or directory).
Fails because cortexm3_rtl/ is not present in the downloaded ARM designStart files.
...I did look at posts and cortxm3_model/libcortexm3_integrationds_dsm.a and cortxm3_model/libcarbon5.so are present. This seems to be a different problem than others were facing.
...I did add my license file (did this after my download of DesignStart) ...Is there a different download which contains the cycle models?
I've just ran the exact same command you are using with Cadence Xcelium 19.09-s007 and get the exact same message as you:
However, I was able to compile and got the following message after compilation:
>> Testbench compile with ius and DSM=yes completed successfully, log in ius_compile.log
PS. I was subsequently able to successfully run the "hello" test.