- Our product need power management with cortex M0.
- In the verilog cod we request from ARM, there is a output pin "GATEHCLK" In module CORTEXM0INTEGRATION,but it is floating. I think it is used for power management.
How should this output pin "GATEHCLK" be connected?
1. Could PCLK be gated by GATEHCLK? I found that PCLK is running in sleeping/deepsleeping.
2. I run verilog simulation and found that GATEHCLK is posedge driven. Should I modify as below
to avoid transitional hazards?