- Our product need power management with cortex M0.
- In the verilog cod we request from ARM, there is a output pin "GATEHCLK" In module CORTEXM0INTEGRATION,but it is floating. I think it is used for power management.
How should this output pin "GATEHCLK" be connected?
The GATEHCLK output (available at the Cortex-M0 Integration level) is intended to be used to safely gate HCLK when the SLEEPING signal is asserted and no debugger is connected.
Would you please explain more detailed?
SLEEPING output is asserted when the processor goes into sleep-now (WFE, WFI) or sleep-on-exit. SLEEPDEEP output is asserted when SLEEPING is asserted and if the SLEEPDEEP bit of the System Control Register has previously been set.
SLEEPING may indicate some level of external power saving (or none), but would typically be a state from which wake-up could quickly occur. For example, HCLK could be suppressed (though FCLK would need to be running to identify the wakeup event).
SLEEPDEEP is intended to request deeper power-saving modes, such as switching off external components such as a PLL, which would imply a longer wake-up time before the processor could respond to a wake-up event. SLEEPDEEP is only an indication to the external system; the processor does not distinguish at all between SLEEPING alone and SLEEPING with SLEEPDEEP.
If you are looking for signal that indicates that it is safe to turn off the clock when the core is sleeping, then GATEHCLK output (available at the Cortex-M0+ Integration level) is intended to be used to safely gate HCLK when the SLEEPING signal is asserted and no debugger is connected.
GATEHCLK is defined as:
(SLEEPING | ~SLEEPHOLDACKn) & ~CDBGPWRUPACK
CDBGPWRUPREQ request your power and clock controller to restore power and clocks to the Debug bus domain. The corresponding CDBGPWRUPACK signal is asserted by your power and clock controller once the respective domain has power and clocks restored. If you are not using power or clock gating on your chip, feed each REQ back to the corresponding ACK.
1. Could PCLK be gated by GATEHCLK? I found that PCLK is running in sleeping/deepsleeping.
2. I run verilog simulation and found that GATEHCLK is posedge driven. Should I modify as below
to avoid transitional hazards?