Hello,
I am trying to bring up Cortex M0 on Arty-A7 FPGA board from Digilent. I use Vivado 19.1 and 18.3 version. IN both version, I get the following error,
ERROR: [IP_Flow 19-3461] Value 'reset' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)' for BD Cell 'Clocks_and_Resets/proc_sys_reset_base' . Valid values are - CustomINFO: [IP_Flow 19-3438] Customization errors found on 'Clocks_and_Resets/proc_sys_reset_base'. Restoring to previous valid configuration.ERROR: [IP_Flow 19-3439] Failed to restore IP 'Clocks_and_Resets/proc_sys_reset_base' customization to its previous valid configuration.ERROR: [Common 17-39] 'set_property' failed due to earlier errors.ERROR: [BD 41-1273] Error running post_propagate TCL procedure: ERROR: [Common 17-39] 'set_property' failed due to earlier errors. ::xilinx.com_ip_proc_sys_reset_5.0::post_propagate Line 23WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_0> to default.ERROR: [BD 41-241] Message from IP propagation TCL of /Clocks_and_Resets/proc_sys_reset_base: set_property error: Value 'reset' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)' for BD Cell 'Clocks_and_Resets/proc_sys_reset_base' . Valid values are - CustomCustomization errors found on 'Clocks_and_Resets/proc_sys_reset_base'. Restoring to previous valid configuration.Failed to restore IP 'Clocks_and_Resets/proc_sys_reset_base' customization to its previous valid configuration.
Please help me understand this error and how to go fix it/or go around it.
Even I am getting the same error. Did you clear those error. If you got it let me know how to clear those error. I am using vivado 2019.2
I think this is the same error I had when I didn't install the board files (section 2.1 of the DesignStart user guide).
In my case I didn't think I needed the board files since I wasn't targeting the Arty board. But after I installed the board files, after a clean unpack of the DesignStart bundle, the errors went away.
Works with Vivado 2018.3 and 2019.1. Beware that with 2019.2 onwards, the Xilinx SDK appears quite different, probably best to stick with one of the earlier versions.