ERROR: [IP_Flow 19-3461] Value 'reset' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)' for BD cell

Hello,

I am trying to bring up Cortex M0 on Arty-A7 FPGA board from Digilent. I use Vivado 19.1 and 18.3 version. IN both version, I get the following error,

ERROR: [IP_Flow 19-3461] Value 'reset' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)' for BD Cell 'Clocks_and_Resets/proc_sys_reset_base' . Valid values are - Custom
INFO: [IP_Flow 19-3438] Customization errors found on 'Clocks_and_Resets/proc_sys_reset_base'. Restoring to previous valid configuration.
ERROR: [IP_Flow 19-3439] Failed to restore IP 'Clocks_and_Resets/proc_sys_reset_base' customization to its previous valid configuration.
ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
ERROR: [BD 41-1273] Error running post_propagate TCL procedure: ERROR: [Common 17-39] 'set_property' failed due to earlier errors.
::xilinx.com_ip_proc_sys_reset_5.0::post_propagate Line 23
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_0> to default.
ERROR: [BD 41-241] Message from IP propagation TCL of /Clocks_and_Resets/proc_sys_reset_base: set_property error: Value 'reset' is out of the range for parameter 'RESET BOARD INTERFACE(RESET_BOARD_INTERFACE)' for BD Cell 'Clocks_and_Resets/proc_sys_reset_base' . Valid values are - Custom
Customization errors found on 'Clocks_and_Resets/proc_sys_reset_base'. Restoring to previous valid configuration.
Failed to restore IP 'Clocks_and_Resets/proc_sys_reset_base' customization to its previous valid configuration.

Please help me understand this error and how to go fix it/or go around it. 

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