Issue with synthesizing Cortex-M0 memory Verilog code

Hi,

We are working to implement the Cortex-M0 processor on silicon in an XFAB 180nm process for one of our products. We have downloaded and synthesized the Verilog code for the example processor "cmsdk_mcu.v", but have encountered some issues. The software seems to crash if the RAM and ROM memories are included. This occurs even if the memory modules are synthesized separately. We are unsure whether this is an issue due to the pdk we are using or if it is simply a customization setting we are missing. We also have questions on whether there is any I2C or ADC modules included in the Verilog code. Any guidance you (or anyone else) can give us in this area would be appreciated.