We are working to implement the Cortex-M0 processor on silicon in an XFAB 180nm process for one of our products. We have downloaded and synthesized the Verilog code for the example processor "cmsdk_mcu.v", but have encountered some issues. The software seems to crash if the RAM and ROM memories are included. This occurs even if the memory modules are synthesized separately. We are unsure whether this is an issue due to the pdk we are using or if it is simply a customization setting we are missing. We also have questions on whether there is any I2C or ADC modules included in the Verilog code. Any guidance you (or anyone else) can give us in this area would be appreciated.
Hi, can you make sure that you have replaced ROM/RAM model according to your synthesized lib? you must guarantee they have same name and ports with original RAM/ROM model, or you have modified RTL code according to the RAM/ROM model in synthesized lib to ensure that the instantiation is correct.
I checked my synthesized lib and it is correct. Also, I checked the name and the ports. I didn't change any name or any ports in there.