How to run the system with a slow clock

Hi,

According ARM® Cortex®-M3 DesignStart  Eval FPGA User Guide, ch. 4.2, 
it should be possible to set OSC0 value from 2MHz to 230MHz,

But setting to a lower frequency than 25 Mhz seems not to work. The log.txt file says

Setting clock 0 to default 25MHz
OSCCLK config: PASSED

What is going  wrong here? Or is that intended and the documentation is wrong.

Meanwhile I found a workaround. I set the CPU clock PLL divider to a bigger value. Is this a valid approach? 

Best Regards,

Rainer