I have synthesized cortex-M3 softcore processor on my Zynq Ultrascale+ Evaluation board and it works fine. As of now, I have connected JTAG pins to the FPGA I/O pins and using J-Link debugger to debug the softcore. Since, I have limited FPGA pins available on board. I want to use the available JTAG pins in order to debug all the cores with one debugger.
I would like to create a JTAG daisy chain between Coertex A53, Cortex R5 and Cortex M3 processors so that I could use same JTAG to debug all the available processors on board.
Is it possible to do it with Cortex M3. Could you please suggest a way to do it efficiently? Joseph Yiu Sean Houlihane
I look forward for your reply
For ASIC/SoC design it is straight forward to do that in RTL designs, but unfortunately I don't know much about the Zynq platform and don't know if it is easy to define the JTAG signal routing for the Cortex-A53 and Cortex-R5. You might need to ask this in Xilinx forum (https://forums.xilinx.com/).
Like Joseph has indicated, it might be better to direct the board related questions to the Xilinx forums. However, from your description, it's not clear whether you have a full CoreSight (e.g. CoreSight SoC 400) to integrate all 3 cores. If its simply getting a JTAG daisy chain on the board running with the different cores already on the board your best bet is with Xilinx I suspect.