Enabling SWO output in Cortex M3 DesignStart FPGA Xilinx edition?

Is it possible to enable SWO from software, as discussed here for example? Without the DAPlink board?

I've been able to successfully enable the parallel trace port, but am not having any success getting SWO working.

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  • Follow-up question that hopefully is easier to answer: in the Xilinx DesignStart Cortex M3, which pin (if any) of the Cortex M3 carries SWO?

    The Cortex M3 instance has ports for SWCLK, SWDI, SWDO, and SWDOEN, but I don't see an SWO port.

    I am able to do SWD debugging with a J-Link debugger. I can also enable SWO tracing, but ITM_Print's don't produce any sign of life.

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  • Follow-up question that hopefully is easier to answer: in the Xilinx DesignStart Cortex M3, which pin (if any) of the Cortex M3 carries SWO?

    The Cortex M3 instance has ports for SWCLK, SWDI, SWDO, and SWDOEN, but I don't see an SWO port.

    I am able to do SWD debugging with a J-Link debugger. I can also enable SWO tracing, but ITM_Print's don't produce any sign of life.

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