m3 for xilinx,I want to change the ip named aix_quad_spi_0 into the standard spi for a spi tft display,what should I change the io timing part in the xdc file?

when i just change the related io timing part about axi_quad_spi_0 a little like following text,I came out a critical warming about timing.

#Timing
#Output clocks
#Base SPI
create_generated_clock -name base_spi_clk -source [get_pins -hierarchical -filter {NAME =~ m3_for_arty_a7_i/axi_quad_spi_0/sck_o}] -divide_by 1 [get_ports spi_sck*]

#IO timings
#Base SPI

set base_spi_od_Tsu 2.0
set base_spi_od_Thd -2.5
set base_spi_id_Tco 8.5
set base_spi_id_Tho 2.0

#cs
set_output_delay -clock [get_clocks base_spi_clk] -max -add_delay $base_spi_od_Tsu [get_ports {spi_ss*}]
set_output_delay -clock [get_clocks base_spi_clk] -min -add_delay $base_spi_od_Thd [get_ports {spi_ss*}]

#miso
set_input_delay -clock [get_clocks base_spi_clk] -max -add_delay $base_spi_id_Tco [get_ports {spi_io1_io}]
set_input_delay -clock [get_clocks base_spi_clk] -min -add_delay $base_spi_id_Tho [get_ports {spi_io1_io}]

#mosi
set_output_delay -clock [get_clocks base_spi_clk] -max -add_delay $base_spi_od_Tsu [get_ports {spi_io0_io}]
set_output_delay -clock [get_clocks base_spi_clk] -min -add_delay $base_spi_od_Thd [get_ports {spi_io0_io}]