I'm using a Pynq-Z1 board in which i'm trying to read the DDR memory of the PS with a Cortex M1 that is on the PL directly, without a CDMA or an intermediate BRAM
(This is the diagram i'm using. The relevant IPs are the highlighted ones)
My approach is to use a High-Performance slave port of the PS to be accessed by the Cortex M1 (acting as a master), so in the address editor a indicate that the HP0_DDR_LOWOCM is on the peripheral address of the M1 (0x6000000).
The problem is that when i try to read that address (0x60000000) the axi interconnect placed between the M1 and the PS doesn't translate the address from 0x60000000 to 0x00100000 (Where the DDR address is placed on the PS) and the M1 execution stops.
I did the same test placing the HP0_DDR_LOWOCM in the other regions of the M1 memory map but i get always the same problem. If i place it on the peripheral region the axi doesn't translate the address. In the other regions the AXI don't even output any address on the other side...
Do someone know what is the problem and how could i solve it?
I'm thinking about placen an ip that modifies the AXI Interconnect output address changing it from 0x60000000 to 0x00100000, but i was wondering if there is a better solution, maybe modifing some properties on the Keil IDE...
Thanks in advance,
I found out that only way to achive this is by creating a dummy block where you select the Base_address of the RAM on the PS (0x00100000), the Base_address of the RAM of the CM1 (0x60000000) and the range so the block connect all the signals of an axi slave with the ones of an axi master but translating from 0x60000000 to 0x00100000.
If you then take care of disable the caches on the A9 you be successful.