How to load the program into the FPGA ROM block is connected to the I/Dcode Bus ?

Hi,

I'm doing a SOC design by using Desgn Start - Eval version for Cortex-M3(AT421-MN-80001-r0p0-02rel0).And I use the block ROM as the Flash ROM and RAM for the core.After finished a simple Cortex-M3 system just includes the core, ROM , RAM , and debug/reset control module(handle the LOCKUP and SYSRESETREQ signal), I run the simulation with a simple C program :

#include <stdint.h>
int main(void)
{
    static uint32_t i=0;
    while(1)i++;

}

I load the .hex file into ROM by using system function $readmemh,and it's realy work in the simlulation:

The data at the 0x20000000 is increasing in the simulation.Then I program the sysytem into the FPGA,A735T,and use STlink V2 to connect the FPGA board and Keil5.14.Keil can detect the ARM CoreSight,but I can't use STlink to download the C program into the ROM.Download is resulted in to Error : Cannot Write to RAM for Flash Algorithms.

    And the system doesn't run in the FPGA I guess.

And,my classmate is doing a SOC design by using Desgn Start - Eval version too.His system is similar to mine, but the Verilog core to implement AHB and other conctrol is different. We run the simlulation with the same C program and we get the same result.But his system can run in the FPGA and the STlink can detect the core and finish the downlaod with same setting.

This is my Verilog core :

module AHB2MEM #(
    parameter AW = 15,
    parameter start_up = 1
    )               
(
    input wire           HSEL,
    input wire           HCLK,
    input wire           HRESETn,
    input wire           HREADY,
    input wire  [AW-1:0] HADDR,
    input wire     [1:0] HTRANS,
    input wire           HWRITE,
    input wire     [2:0] HSIZE,
    input wire    [31:0] HWDATA,
    output wire          HREADYOUT,
    output wire    [31:0] HRDATA,
    output wire    [1:0] HRESP
);

    assign HREADYOUT = 1'b1; // Always ready
    assign HRESP =2'b0; // Always Okay
    
    // Memory Array
    reg  [31:0] memory[0:((32'h1<<(AW-2))-1)];
    
    initial
        begin
            if (start_up) 
                (*rom_style="block"*) $readmemh("CM3code.hex",memory);//CM3_exmaple.hex,code.hex
        end
     
    // Registers to store Adress Phase Signals
    reg           buf_write;
    reg           buf_read;
    reg  [AW-1:0] buf_hwaddr;
    reg     [2:0] buf_sizes;
    reg     [3:0] buf_sta;
   
    // Sample the Address Phase   
    always @(posedge HCLK or negedge HRESETn)
        begin
            buf_write  <= HRESETn & HREADY & HSEL & HWRITE & HTRANS[1] ;
            buf_read   <= HRESETn & HREADY & HSEL & ~HWRITE & HTRANS[1];

            buf_hwaddr <= HRESETn ? HADDR : 32'b0;

            buf_sizes[0] <= ~HSIZE[1] & ~HSIZE[0];
            buf_sizes[1] <= ~HSIZE[1] & HSIZE[0];
            buf_sizes[2] <= HSIZE[1] ;
            
            buf_sta[0] <= ~HADDR[1] & ~HADDR[0];
            buf_sta[1] <= ~HADDR[1] & HADDR[0];
            buf_sta[2] <= HADDR[1] & ~HADDR[0];
            buf_sta[3] <= HADDR[1] & HADDR[0];         
            
        end
    
    // Read and Write Memory
    always @ (posedge HCLK)
        begin
            
            memory[buf_hwaddr[AW-1:2]][7:0]  <=  (buf_write & (buf_sta[0] & (buf_sizes[0] | buf_sizes[1] | buf_sizes[2] ))) ? HWDATA[7:0] : memory[buf_hwaddr[AW-1:2]][7:0];
            memory[buf_hwaddr[AW-1:2]][15:8] <=  (buf_write & (buf_sta[1] & buf_sizes[0])) ? HWDATA[7:0]:
                                                 (buf_write & (buf_sta[0] & (buf_sizes[1] | buf_sizes[2] ))) ? HWDATA[15:8] : memory[buf_hwaddr[AW-1:2]][15:8];
            memory[buf_hwaddr[AW-1:2]][23:16] <= (buf_write & (buf_sta[2] & (buf_sizes[0] | buf_sizes[1])))  ? HWDATA[7:0]:
                                                 (buf_write & (buf_sta[0] & buf_sizes[2])) ? HWDATA[23:16] : memory[buf_hwaddr[AW-1:2]][23:16];
            memory[buf_hwaddr[AW-1:2]][31:24] <= (buf_write & (buf_sta[3] & buf_sizes[0])) ? HWDATA[7:0]:
                                                 (buf_write & (buf_sta[2] & buf_sizes[1])) ? HWDATA[15:8]:
                                                 (buf_write & (buf_sta[0] & buf_sizes[2])) ? HWDATA[31:24] : memory[buf_hwaddr[AW-1:2]][31:24];                                     
        end
   assign HRDATA = memory[buf_hwaddr[AW-1:2]];
endmodule

And this is my classmate's:

module AHB2ROM
#(parameter AW = 15)
(
			input wire HSEL,
			input wire HCLK,
			input wire HRESETn,
			input wire HREADY,
			input wire [31:0] HADDR,
			input wire [1:0] HTRANS,
			input wire HWRITE,
			input wire [2:0] HSIZE,
			input wire [31:0] HWDATA,
			output wire HREADYOUT,
			output wire [31:0] HRDATA,
			output wire    [1:0] HRESP
);


  assign HREADYOUT = 1'b1; // Always ready
  assign HRESP =2'b0; // Always Okay

// Registers to store Adress Phase Signals
 
  reg APhase_HSEL;
  reg APhase_HWRITE;
  reg [1:0] APhase_HTRANS;
  reg [31:0] APhase_HADDR;
  reg [2:0] APhase_HSIZE;

// Memory Array  
  reg  [31:0] memory[0:((32'h1<<(AW-2))-1)];
  
  initial
  begin
    (*rom_style="block"*) $readmemh("CM3code.hex",memory);//CM3_exmaple.hex,code.hex
  end

// Sample the Address Phase   
  always @(posedge HCLK or negedge HRESETn)
  begin
	 if(!HRESETn)
	 begin
		APhase_HSEL <= 1'b0;
      APhase_HWRITE <= 1'b0;
      APhase_HTRANS <= 2'b00;
		APhase_HADDR <= 32'h0;
		APhase_HSIZE <= 3'b000;
	 end
    else if(HREADY)
    begin
      APhase_HSEL <= HSEL;
      APhase_HWRITE <= HWRITE;
      APhase_HTRANS <= HTRANS;
		APhase_HADDR <= HADDR;
		APhase_HSIZE <= HSIZE;
    end
  end

// Decode the bytes lanes depending on HSIZE & HADDR[1:0]

  wire tx_byte = ~APhase_HSIZE[1] & ~APhase_HSIZE[0];
  wire tx_half = ~APhase_HSIZE[1] &  APhase_HSIZE[0];
  wire tx_word =  APhase_HSIZE[1];
  
  wire byte_at_00 = tx_byte & ~APhase_HADDR[1] & ~APhase_HADDR[0];
  wire byte_at_01 = tx_byte & ~APhase_HADDR[1] &  APhase_HADDR[0];
  wire byte_at_10 = tx_byte &  APhase_HADDR[1] & ~APhase_HADDR[0];
  wire byte_at_11 = tx_byte &  APhase_HADDR[1] &  APhase_HADDR[0];
  
  wire half_at_00 = tx_half & ~APhase_HADDR[1];
  wire half_at_10 = tx_half &  APhase_HADDR[1];
  
  wire word_at_00 = tx_word;
  
  wire byte0 = word_at_00 | half_at_00 | byte_at_00;
  wire byte1 = word_at_00 | half_at_00 | byte_at_01;
  wire byte2 = word_at_00 | half_at_10 | byte_at_10;
  wire byte3 = word_at_00 | half_at_10 | byte_at_11;

// Writing to the memory

// Student Assignment: Write a testbench & simulate to spot bugs in this Memory module

  always @(posedge HCLK)
  begin
	 if(APhase_HSEL & APhase_HWRITE & APhase_HTRANS[1])
	 begin
		if(byte0)
			memory[APhase_HADDR[AW-1:2]][7:0] <= HWDATA[7:0];
		if(byte1)
			memory[APhase_HADDR[AW-1:2]][15:8] <= HWDATA[15:8];
		if(byte2)
			memory[APhase_HADDR[AW-1:2]][23:16] <= HWDATA[23:16];
		if(byte3)
			memory[APhase_HADDR[AW-1:2]][31:24] <= HWDATA[31:24];
	  end
  end

// Reading from memory 
  assign HRDATA = memory[APhase_HADDR[AW-1:2]];
  
endmodule

I found other similar questions' answers,and I try to use DAPlink to do the same thing but it still do not work in my program.I check that the CDBGPWRUPREQ and  CDBGPWRUPACK port are connected.Could any one tell me what the problem happens?Why my classmate's CortexM3 system can work without any Flash Algorithms but mine cannot?

Thanks,

Chan

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