Hi,I am trying to set up the synthesis environment for Cortex M0 and I have downloaded the FE part of the library from your website. However, according to the tech setup script (cmsdk_mcu_system_tech.tcl), it seems I am missing a folder which contains the following files:/tsmc/ce018fg/star-rcxt/1p6m/t018mm_1p6m_tf2itf.map/tsmc/ce018fg/star-rcxt/1p6m/t018mm_1p6m.tluplus
I have tried to use /tsmc/star-rcxt/t018s6ml_tf2itf.map and /tsmc/ce018fg/arm_tech/r5p1/synopsys_tluplus/6lm/typical.tluplus which I was able to find on another package but it seems like I am getting the following errors when synthesising:1. Checking the conducting layer names in ITF and mapping file ... Error: Layer "METAL1" (metal1) exists in the MW-tech but not in the mapping AND ITF file. (TLUP-001)Error: Layer "METAL2" (metal2) exists in the MW-tech but not in the mapping AND ITF file. (TLUP-001)Error: Layer "METAL3" (metal3) exists in the MW-tech but not in the mapping AND ITF file. (TLUP-001)Error: Layer "METAL4" (metal4) exists in the MW-tech but not in the mapping AND ITF file. (TLUP-001)Error: Layer "METAL5" (metal5) exists in the MW-tech but not in the mapping AND ITF file. (TLUP-001)Error: Layer "METAL6" (metal6) exists in the MW-tech but not in the mapping AND ITF file. (TLUP-001)Error: Failed to load TLUPlus files. They may be corrupted. (TLUP-039)
Therefore, I think that this is the reason why my synthesis fails and I cannot get any area/power results for the MCU.
Could you please let me know where I can find the right .map and .tluplus files so that I can proceed with the synthesis as soon as possible?
Thanks in advance,Nacho
I asked an expert on this and he gave me the following answer. Hope this helps.
The itf2map file is there to map between the layer naming which is used in the cell library and that which is used in the foundry extraction deck. Because the mapping file is one they have found with the extraction deck (tluplus, which is derived from itf) I would expect the column for the extraction deck to be correct and the library column to need updating.
Techfile (library) conductor names are in the left column, whilst extraction deck (tluplus/itf) conductor names are in the right hand column.
If they update the left hand column of **/t018s6ml_tf2itf.map they have found to use the same naming as they have in the LEF in the libraries area then it _should_ be happier.
This should help them to understand the layer names which are to be used on the tf side.
grep LAYER <lef file> | grep -v ANTENNA |sort -u
Example type of change:
Hi Joseph,Thank you so much for your reply - I really appreciate it.I am afraid I am getting different kind of errors now and I am getting very confused as it is my first time trying to synthesise such a design and it is overwhelming.
The only thing I currently need, however, is the total area of the synthesised M0 with all the default settings. Is there any chance you could run synthesis using CE018FG and the default scripts, and attach the area report? It would mean the world to me.Thank you very much for all your help in advance, Nacho
For that you need to contact product manager as I cannot put the data here. Please use the form on
Perfect, thank you so much.
You might need to highlight to the team that deal with the request that you already have signed up Cortex-M0 DesignStart and has access to RTL - but you want to get the data because of problem in synthesis. Otherwise the web response team might ask you to try out DesignStart :-)