I am trying to debug the m3 IP core on Xilinx ARTRIX FPGA through SWD.
I just try to debug the none axi peripheral core (only runs some assembler to control general register)
This is the port configuration of IP core.
And, this is some reset configuration:
Then, Keil can successfully readout the IDCODE of M3:
Finally, my problem come out:
For single core design you can tie DBGRESTART to 0. Could you try to see if it helps?
Thanks so much!
This problem are caused by two signals: EDBGRQ and DBGRESTART.
After i fix both signals, the debug works well!