Hi, My name is Juan i'm starting a course in embedded sistemas and I want to have fun with DesignStart. I am interested in FPGA part.
I Just downloaded Cortex-M1 DesignStart FPGA - Xilinx Pkg.
I have Access to a PYNQ-Z1. I'm trying to figure out how to make a simple hello world! Project.
Just configure the Cortex-M1 in the PYNQ-Z1 PL and write a hello world to UART, but i don't know how to achive that...
Could you give me some hints or any information about how to do it?
Thank you for hep.
First of all thanks for answering.
I found what I was doing wrong, so now by using the Keil u vision tool chain for software development I’m able to run code in the CM1.
But now I have another issue...
I’m trying to communicate the A9 from the PS with the CM1 from the PL using the AXI HP interface to access the DDR(used as shared memory).
My idea is to run a simple code in the CM1 (using Keil) that put a 1 or a 0 in the first DDR address of the PS through the AXI HP port so by running another simple code in the A9 (using the Vivado SDK) it could read that first address of the DDR and toggle a LED (connected through AXI_GPIO) depending on its value.
I’m able to generate the bitstream without problems, then I export the hardware and launch the sdk. I’m also able to generate a BPS for the CM1 (for its further software development) but when I generate another BPS with the A9 processor set as the CPU it has like 100 not file found or unresolved inclusion (I try to add the include paths, clean.. but nothing). But if I generate another BPS with the CM1 as the CPU I got no problem...
Could you, or someone help me with this issue?
Thanks in advance,
Sorry for the delay. Unfortunately I don't have the answer for this one. Have you tried contact Xilinx support?
I found out what was the issue so i'm gonna answer below in case you have the same problem:
When generating the BSP for the CM1 you have to select the ARM_SW_IP_REPOSITORY (that comes with the CM1 software) as a repository in Xilinx > Repositories on the SDK.
But when you make the BSP for the A9 you have to delete that from there, otherwise you wouldn't be able to generate correctly the A9 BSP.
So I suggest to first generate the A9 BSP, then mark ARM_SW_IP_REPOSITORY as a repository in Xilinx > Repositories and then generate the CM1 BSP. That must work properly.
Hope you find it useful,