I'm trying to load the block diagram for the arty a7 M1 example project. I get this error:
[BD 41-1712] The specified IP 'xilinx.com:ip:axi_bram_ctrl:4.0' does not support the current part 'xc7a35ticsg324-1L'
Any thoughts on how to get past this? Weirdly, the Xilinx docs for that IP seem to support the idea that it's not supported on the xc7a35 part.
Hi, I had the same problem with Vivado 2018.3. You can try 2018.2 - it worked for me. The reason of error might be a version of axi_bram_ctrl IP core - 2018.2 supports 4.0, while 2018.3 supports 4.1. But I have not verified it yet...