I'm trying to load the block diagram for the arty a7 M1 example project. I get this error:
[BD 41-1712] The specified IP 'xilinx.com:ip:axi_bram_ctrl:4.0' does not support the current part 'xc7a35ticsg324-1L'
Any thoughts on how to get past this? Weirdly, the Xilinx docs for that IP seem to support the idea that it's not supported on the xc7a35 part.
Thanks! It works for me with Vivado 2019.1