Hi. First of all, thanks for your attention in advance. I have to say that I am completely new in FPGA programming, but I could have never imagined that running an example with a documentation explaining it step by step could be so cumbersome and error prone.
I downloaded DesignStart Cortext M-3 for Arty A35T. So far I had problems with executables dissapearing because of antivirus and things not working well caused by some firewall rules.
Once I could add the IPs to the repository, my first problem was opening the design diagram. It seems that there was a controller called AXI_BRAM that was on its version 4.1 in the newews Vivado 2018.3, but the design was using 4.0. I did not know how to handle that or change it, so I edited in a text editor the file and changed it by hand. Not sure if this is the intended way of solving this things, but it helped. I would like here to thank to anyone that can point me to the correct way of doing this change using Vivado.
Then I tried to run synthesis, and I have several problems caused by some definitions (constraints) of the DAPLink. I managed to disable constraints for synthesis and seem to work (Also commented all 3 corresponing defines in the testbench definition file of the project). Then I had the problem making the run, and here I am completely lost, because there are some errors about timings not met.
Before putting here so many message logs, I would like to know if there is someone that has the same SO, same Vivado version and same or very similar FPGA development board (without DAPLink) that has acomplished to reach the generation of bitstream to upload into the chip.
Before finishing, I can say that before the synthesis and implementation, I uploaded the original bit stream and it worked. Connected using moba xterm serial console and tested the buttons. Now I would like to be able to generate my own bitstream and run it as well.