In our product, cortex-m0 is internal digital block1. After synthesis, inout ports such as P0, P1, will be inferred as tri-state logic(TLAT). Is it ok? or please provide the recommanded method.2. For scan chain insertion, additional independent input "scan enable" is necessary. However there is no extra pin assgin for it in our design. Please let me know if there is any solution.
I have another question:
In our design,
1. reset in generated from POR circuit through a counter.
2. For scan chain insertion, scan signal "test_en" is set by internal register.
3. some reset signals to flip-flops are generated by another flip-flop(s).
The question is : additional independent input "scan_reset" is necessary to apply to all flip-flops. However there is no extra pin assgin for it in our design. Please let me know if there is any solution.
>reset in generated from POR circuit through a counter.
If I understand you correctly you plan to omit a top level power-on-reset and try to use an internal counter (that doesn't has reset) to generate a reset pulse. That is undesirable for most ASIC designs that have internal oscillators - you possibly won't be able to guarantee that the reset's de-assertion happens after the clock is stabilized. (i.e. If the processor came out of reset when the clocks are still unstable, your system might not be reset correctly.)