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Xilinx FPGA Block ROM is used as FLASH and how to load the program in to this?

vbandaaru
Offline over 2 years ago

Hi,

I am using the SoC design from Desgn Start - Eval version for Cortex-M0 with only modification of using Xilinx Block ROM as the Memory for FLASH ROM as well as for RAM.

And my goal is to load the application into the FLASH ROM (Xilinx Block ROM) using KEIL-ULINK2.

Though KEIL-ULINK2 is able to detect the JTAG/SWD device and display the IDCODE, 

Download is resulted in to Error :  ' Device could not be powered up'  , 'Flash Download failed - Target DLL has been cancelled'

Could any one with the knowledge of this, please let me know what is the issue and how to resolve it.

Thanks for your time and help.

Regards,
Venkat

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  • +1 Offline over 2 years ago

    Please check the connections of    CDBGPWRUPREQ and  CDBGPWRUPACK,
    Typically you can connect it as

    CDBGPWRUPREQ -> D flip-flop (FCLK) -> D flip-flop (FCLK) -> CDBGPWRUPACK

    In ASIC design this request-acknowledge handshaking allows debugger connection to wait a little bit until debug logic wake up (for power saving). In FPGA you can just feedback the req to ack with a simple synchroniser.

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  • +1 Offline over 2 years ago

    Please check the connections of    CDBGPWRUPREQ and  CDBGPWRUPACK,
    Typically you can connect it as

    CDBGPWRUPREQ -> D flip-flop (FCLK) -> D flip-flop (FCLK) -> CDBGPWRUPACK

    In ASIC design this request-acknowledge handshaking allows debugger connection to wait a little bit until debug logic wake up (for power saving). In FPGA you can just feedback the req to ack with a simple synchroniser.

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