I am using the SoC design from Desgn Start - Eval version for Cortex-M0 with only modification of using Xilinx Block ROM as the Memory for FLASH ROM as well as for RAM.
And my goal is to load the application into the FLASH ROM (Xilinx Block ROM) using KEIL-ULINK2.
Though KEIL-ULINK2 is able to detect the JTAG/SWD device and display the IDCODE,
Download is resulted in to Error : ' Device could not be powered up' , 'Flash Download failed - Target DLL has been cancelled'
Could any one with the knowledge of this, please let me know what is the issue and how to resolve it.
Thanks for your time and help.
Please check the connections of CDBGPWRUPREQ and CDBGPWRUPACK,Typically you can connect it as
CDBGPWRUPREQ -> D flip-flop (FCLK) -> D flip-flop (FCLK) -> CDBGPWRUPACK
In ASIC design this request-acknowledge handshaking allows debugger connection to wait a little bit until debug logic wake up (for power saving). In FPGA you can just feedback the req to ack with a simple synchroniser.
Joseph, Thanks for the reply.
After modifying the logic as mentioned , I don't get the error message.
Recently I've been using the cortex M3 designstart eval . I have a question whether the design process and the executing process of this tool (the eval) is suitable for xilinx vivado platform. casue I've read some sheets that are runs and examples in quartus for altera.
Yes. Last year we published a e-book and that comes with an example using Cortex-M3 DesignStart Eval with Vivado. Please visit https://pages.arm.com/socrefbook.html